8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
396 ILL F06.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
396 ILL F08.2
Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19
20
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71146-03-000 6/01 396
15
SST [ SILICON STORAGE TECHNOLOGY, INC ]
