8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
55
A0
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
396 ILL F04.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
396 ILL F05.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71146-03-000 6/01 396
14
SST [ SILICON STORAGE TECHNOLOGY, INC ]
