64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
PACKAGING DIAGRAMS
7.40
7.60
10.00
10.65
Pin #1
Identifier
10.08 †
10.50
.020x45°
7°
4 places
7°
4 places
2.35
2.65
.33
.51
.23
.32
.10
.30
.38 ‡
1.27
1.27 BSC
Note:
1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is 10.10; SST min (10.08) is less stringent
‡ = JEDEC min is 0.40; SST min (0.38) is less stringent
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 ( .05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
16.soic-SC-ILL.3
FIGURE 29: 16-Lead Plastic Small Outline Integrated Circuit (SOIC)
SST Package Code SC
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
29
SST [ SILICON STORAGE TECHNOLOGY, INC ]
