64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V
in less than 300 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is required. The recom-
mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset. See Table 14
and Figures 26 and 27 for more information.
TABLE 14: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
1
TPU-WRITE
100
µs
T14.0 1392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
T
PU-READ
V
min
V
DD
DD
0V
V
IH
RESET#
CE#
T
RECR
1203 F37.0
Note: See Table 2 on page 5 for TRECR parameter.
FIGURE 26: Power-Up Reset Diagram
V
DD
V
Max
DD
Chip selection is not allowed.
All commands are rejected by the device.
V
Min
DD
T
T
PU-READ
PU-WRITE
Device fully accessible
Time
1392 F26.0
FIGURE 27: Power-up Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
26
SST [ SILICON STORAGE TECHNOLOGY, INC ]
