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SST25VF064C-80-4C-SAE 参数 Datasheet PDF下载

SST25VF064C-80-4C-SAE图片预览
型号: SST25VF064C-80-4C-SAE
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位的SPI串行双I / O闪存 [64 Mbit SPI Serial Dual I/O Flash]
分类和应用: 闪存
文件页数/大小: 31 页 / 903 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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64 Mbit SPI Serial Dual I/O Flash  
SST25VF064C  
Data Sheet  
TABLE 12: Reliability Characteristics  
Symbol  
Parameter  
Endurance  
Data Retention  
Latch Up  
Minimum Specification  
Units  
Test Method  
1
NEND  
10,000  
100  
Cycles JEDEC Standard A117  
1
TDR  
Years  
mA  
JEDEC Standard A103  
JEDEC Standard 78  
1
ILTH  
100 + IDD  
T12.0 1392  
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
TABLE 13: AC Operating Characteristics  
33 MHz  
50 MHz  
75/80 MHz  
Symbol  
Parameter  
Serial Clock Frequency High-Speed Read  
Serial Clock High Time  
Serial Clock Low Time  
Serial Clock Rise Time (Slew Rate)  
Serial Clock Fall Time (Slew Rate)  
CE# Active Setup Time  
CE# Active Hold Time  
CE# Not Active Setup Time  
CE# Not Active Hold Time  
CE# High Time  
Min  
Max  
33  
Min  
Max  
50  
Min  
Max  
75/80  
Units  
MHz  
ns  
1
FCLK  
TSCKH  
TSCKL  
13  
13  
0.1  
0.1  
5
9
9
6
6
ns  
2
TSCKR  
0.1  
0.1  
5
0.1  
0.1  
5
V/ns  
V/ns  
ns  
TSCKF  
3
TCES  
3
TCEH  
5
5
5
ns  
3
TCHS  
5
5
5
ns  
3
TCHH  
5
5
5
ns  
TCPH  
50  
50  
50  
ns  
4
TCHZ  
CE# High to High-Z Output  
SCK Low to Low-Z Output  
Data In Setup Time  
7
7
7
ns  
TCLZ  
TDS  
0
3
5
5
5
5
5
0
3
5
5
5
5
5
0
2
4
5
5
5
5
ns  
ns  
TDH  
Data In Hold Time  
ns  
THLS  
THHS  
THLH  
THHH  
HOLD# Low Setup Time  
HOLD# High Setup Time  
HOLD# Low Hold Time  
HOLD# High Hold Time  
HOLD# Low to High-Z Output  
HOLD# High to Low-Z Output  
Output Hold from SCK Change  
Output Valid from SCK  
Sector-Erase  
ns  
ns  
ns  
ns  
4
THZ  
7
7
7
7
7
7
ns  
4
TLZ  
ns  
TOH  
TV  
0
0
0
ns  
15  
25  
10  
25  
6
ns  
TSE  
TBE  
TSCE  
TPP  
TPSID  
25  
25  
50  
2.5  
1.0  
ms  
ms  
ms  
ms  
Block-Erase  
25  
50  
2.5  
1.0  
25  
Chip-Erase  
50  
Page-Program  
2.5  
1.0  
Program Security ID  
ms  
T13.1 1392  
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz  
Maximum clock frequency Fast-Read Dual-Output (3BH) is 75 MHz  
Maximum clock frequency Fast-Read Dual I/O (BBH) is 50 MHz  
Maximum clock frequency for High-Speed Read, OBH, is 80 MHz  
Maximum clock frequency for Dual-Input Page-Program, A2H, is 50 Mhz  
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements  
3. Relative to SCK.  
4. Not 100% tested in production.  
©2010 Silicon Storage Technology, Inc.  
S71392-04-000  
04/10  
24  
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