SL15100
Standby Current
ISBC
IOL
PD#=GND
-
80
-
100
15
-
ȝA
ȝA
pF
pF
pF
pF
pF
Output Leakage Current
Pins 6 and 7
-15
Minimum setting value
Maximum setting value
Resolution (programming steps)
Pins 4 and 8
-
-
-
-
-
8.5
40
0.5
4
Programmable
Input Capacitance at
Pins 2 and 3
CXIN
-
CXOUT
-
Input Capacitance
Load Capacitance
CIN2
CL
7
SSCLK/REFCLK , Pins 6 and 7
-
15
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Symbol
FIN1
Condition
Crystal or Ceramic Resonator
External Clock
Min
8
Typ
Max
48
Unit
Input Frequency Range
Input Frequency Range
Output Frequency Range
Output Frequency Range
Output Frequency Range
Output Duty Cycle
-
-
MHz
MHz
MHz
MHz
MHz
%
FIN2
8
166
200
48
FOUT1 SSCLK
3
-
FOUT2 REFCLK, crystal or resonator input
FOUT3 REFCLK, clock input
0.25
0.25
45
45
40
-
-
166
55
DC1
DC2
DCIN
tr/f1
SSCLK
50
50
50
Output Duty Cycle
REFCLK
55
%
Input Duty Cycle
Clock Input, Pin 3
60
%
Programmable, VDD=3.3
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
-
-
-
-
-
-
4.00
2.00
1.40
1.10
0.85
0.70
4.80
2.40
1.70
1.35
1.00
0.85
ns
ns
ns
ns
ns
ns
CL=15pF, 20 to 80% of VDD
tr/f2
tr/f3
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
tr/f4
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
tr/f5
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
tr/f6
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
tr/f7
Programmable, VDD=3.3
-
-
0.55
100
0.67
135
ns
ps
CL=15pF, 20 to 80% of VDD
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ1
CCJ2
CCJ3
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=Off
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=Off
-
-
110
130
145
175
ps
ps
Cycle-to-Cycle Jitter
CLKIN=SSCLK=33MHz, 2%Spread
Rev 1.8, August 10, 2007
Page 9 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
