SL15100
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
CCJ6
CCJ7
CCJ8
CCJ9
CLKIN=SSCLK=33MHz,
2%Spread, REFCLK=On
-
-
-
-
200
90
260
110
140
200
ps
ps
ps
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CLKIN=SSCLK=166MHz,
2%Spread, REFCLK=On
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
110
150
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
tPD
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
-
-
180
3.5
350
5.0
ns
Power-down Time
tPU1
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
ms
Power-up Time
(Crystal or Resonator)
tPU2
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
-
2.0
3.0
ms
Power-up Time
(Clock)
tOE
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
-
180
180
350
350
ns
ns
Output Enable Time
Output Disable Time
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Spread Percent Range
Spread Percent Variation
Modulation Frequency
SPR
SSCLK-1/2
0.25
-15
30
-
-
5.0
15
%
%
ǻSS%
FMOD
Variation of programmed Spread %
Programmable, 31.5 kHz standard
31.5
120
kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description
Operating Voltage
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Voltage
Symbol
VDD
Condition
VDD+/-10%
Min
2.97
0
Typ
Max
3.63
0.3VDD
VDD
Unit
V
3.3
VIL
CMOS Level, Pins 4 and 8
CMOS Level, Pins 4 and 8
IOH=8mA , Pins 6 and 7
IOL=8mA, Pins 6 and 7
-
-
-
-
V
VIH
0.7VDD
VDD-0.5
-
V
VOH1
VOL1
-
V
0.5
V
VIN=VDD, Pins 4 and 8
Input High Current
IIH
-
-
15
ȝA
If no pull-up/down resister used
VIN=GND, Pins 4 and 8
Input Low Current
IIL
-
-
15
ȝA
kȍ
If no pull-up/down resister used
Pull-up or Down Resistor
RPU/D
VIN=VDD or GND
100
160
220
FIN=30MHz, REFCLK=30MHz
SSCLK=66MHz, PD#/OE=VDD
SSON#=GND, CL=0
Operating Supply Current
IDD
-
8.0
9.6
mA
Rev 1.8, August 10, 2007
Page 8 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
