SL15100
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
CCJ8
-
100
130
ps
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
CCJ9
tPD
-
-
-
135
150
3.5
180
350
5.0
ps
ns
Time from PD# falling edge to Hi-Z at
outputs (Asynchronous)
Power-down Time
Power-up Time
Time from PD# rising edge to valid
frequency at outputs (Asynchronous)
tPU1
ms
(Crystal or Resonator)
Power-up Time
(Clock)
Time from PD# rising edge to valid
frequency at outputs (Asynchronous)
tPU2
tOE
-
-
-
2.0
180
180
3.0
350
350
ms
ns
ns
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
Output Enable Time
Output Disable Time
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
tOD
Spread Percent Range
Spread Percent Variation
Modulation Frequency
SPR
SSCLK-1/2 Outputs
0.25
-15
30
-
-
5.0
15
%
%
ǻSS%
FMOD
Variation of programmed Spread %
Programmable, 31.5 kHz standard
31.5
120
kHz
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Description
Operating Voltage
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Voltage
Symbol
VDD
Condition
VDD+/-10%
Min
2.25
0
Typ
Max
2.75
0.3VDD
VDD
Unit
V
2.5
VIL
CMOS Level, Pins 4 and 8
CMOS Level, Pins 4 and 8
IOH=6mA , Pins 6 and 7
IOL=6mA, Pins 6 and 7
-
-
-
-
V
VIH
0.7VDD
VDD-0.5
-
V
VOH1
VOL1
-
V
0.5
V
VIN=VDD, Pins 4 and 8
Input High Current
IIH
-
-
10
ȝA
If no pull-up/down resister used
VIN=GND, Pins 4 and 8
Input Low Current
IIL
-
-
10
ȝA
kȍ
If no pull-up/down resister used
Pull-up/Down Resistors
RPU/D
VIN=VDD or GND
90
160
230
FIN=30MHz, REFCLK=30MHz
SSCLK=66MHz, PD#/OE=VDD
SSON#=GND, CL=0
Operating Supply
Current
IDD
-
6.8
8.1
mA
Standby Current
ISBC
IOL
PD#=GND
-
70
-
90
10
-
ȝA
ȝA
pF
pF
pF
Output Leakage Current
Pins 6 and 7
-10
Minimum programming value
Maximum programming value
Resolution (programming steps)
-
-
-
8.5
40
0.5
Programmable
Input Capacitance at
Pins 2 and 3
CXIN
-
CXOUT
-
Rev 1.8, August 10, 2007
Page 6 of 16