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CYW311OXC 参数 Datasheet PDF下载

CYW311OXC图片预览
型号: CYW311OXC
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™PRO -266 DDR芯片组 [FTG for VIA⑩ Pro-266 DDR Chipset]
分类和应用: 双倍数据速率
文件页数/大小: 18 页 / 250 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CYW311OXC的Datasheet PDF文件第10页浏览型号CYW311OXC的Datasheet PDF文件第11页浏览型号CYW311OXC的Datasheet PDF文件第12页浏览型号CYW311OXC的Datasheet PDF文件第13页浏览型号CYW311OXC的Datasheet PDF文件第14页浏览型号CYW311OXC的Datasheet PDF文件第15页浏览型号CYW311OXC的Datasheet PDF文件第16页浏览型号CYW311OXC的Datasheet PDF文件第18页  
W311  
REF Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
Test Condition/Comments  
Frequency generated by crystal oscillator  
Measured from 0.4V to 2.4V  
Min.  
Typ.  
Max. Unit  
f
14.318  
MHz  
tR  
0.5  
0.5  
45  
2
2
V/ns  
V/ns  
%
tF  
Measured from 2.4V to 0.4V  
tD  
Measured on rising and falling edge at 1.5V  
55  
3
fST  
Frequency Stabilization  
Assumes full supply voltage reached within 1 ms  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
:
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Deviation from 48 MHz  
PLL Ratio  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(48.008 – 48)/48  
Min.  
Typ.  
Max. Unit  
MHz  
f
48.008  
fD  
+167  
ppm  
m/n  
tR  
(14.31818 MHz x 57/17 = 48.008 MHz)  
Measured from 0.4V to 2.4V  
57/17  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
0.5  
0.5  
45  
2
2
V/ns  
V/ns  
%
tF  
Measured from 2.4V to 0.4V  
tD  
Measured on rising and falling edge at 1.5V  
55  
3
fST  
Frequency Stabilization  
Assumes full supply voltage reached within 1 ms  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
:
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)  
Parameter  
Description  
Frequency, Actual  
Deviation from 24 MHz  
PLL Ratio  
Test Condition/Comments  
Determined by PLL divider ratio (see m/n below)  
(24.004 – 24)/24  
Min.  
Typ.  
Max. Unit  
MHz  
f
24.004  
fD  
+167  
ppm  
m/n  
tR  
(14.31818 MHz x 57/34 = 24.004 MHz)  
Measured from 0.4V to 2.4V  
57/34  
Output Rise Edge Rate  
Output Fall Edge Rate  
Duty Cycle  
0.5  
0.5  
45  
2
2
V/ns  
V/ns  
%
tF  
Measured from 2.4V to 0.4V  
tD  
Measured on rising and falling edge at 1.5V  
55  
3
fST  
Frequency Stabilization  
Assumes full supply voltage reached within 1 ms  
ms  
from Power-up (cold start) from power-up. Short cycles exist prior to  
frequency stabilization.  
Zo  
AC Output Impedance  
Average value during switching transition. Used  
for determining series termination value.  
40  
–a  
:
Rev 1.0,November 25, 2006  
Page 17 of 18  
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