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CYW311OXC 参数 Datasheet PDF下载

CYW311OXC图片预览
型号: CYW311OXC
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™PRO -266 DDR芯片组 [FTG for VIA⑩ Pro-266 DDR Chipset]
分类和应用: 双倍数据速率
文件页数/大小: 18 页 / 250 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CYW311OXC的Datasheet PDF文件第6页浏览型号CYW311OXC的Datasheet PDF文件第7页浏览型号CYW311OXC的Datasheet PDF文件第8页浏览型号CYW311OXC的Datasheet PDF文件第9页浏览型号CYW311OXC的Datasheet PDF文件第11页浏览型号CYW311OXC的Datasheet PDF文件第12页浏览型号CYW311OXC的Datasheet PDF文件第13页浏览型号CYW311OXC的Datasheet PDF文件第14页  
W311  
Byte 14: Programmable Frequency Select N-Value Register  
Bit  
Name  
Default  
Description  
Bit 7  
Pro_Freq_EN  
0
Programmable output frequencies enabled  
0 = disabled  
1 = enabled  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_M6  
CPU_FSEL_M5  
CPU_FSEL_M4  
CPU_FSEL_M3  
CPU_FSEL_M2  
CPU_FSEL_M1  
CPU_FSEL_M0  
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W311 will use the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output  
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]  
is updated.  
The setting of FS_Override bit determines the frequency ratio for CPU,  
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same  
frequency ratio stated in the Latched FS[4:0] register. When it is set, W311  
will use the frequency ratio stated in the SEL[4:0] register.  
Byte 15: Reserved Register  
Bit Pin#  
Name  
Default  
Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
47  
6
Latched FS4 input  
Latched FS3 input  
Latched FS2 input  
Latched FS1 input  
Latched FS0 input  
Vendor test mode  
Vendor test mode  
Vendor test mode  
X
X
X
X
X
0
Latched FS[4:0] inputs. These bits are read only.  
7
21  
22  
-
Reserved. Write with ‘0’  
Reserved. Write with ‘1’  
Reserved. Write with ‘1’  
-
1
-
1
Byte 16: Reserved Register  
Bit Pin#  
Name  
Default  
Description  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
-
-
-
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
0
0
0
0
0
0
0
0
Byte 17: Reserved Register  
Bit  
Pin#  
Name  
Default  
Description  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Reserved. Write with ‘0’.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
-
-
-
-
-
-
-
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
Vendor test mode  
0
0
0
0
0
0
0
0
Rev 1.0,November 25, 2006  
Page 10 of 18  
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