W311
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
30
12
12
1
Typ.
–
Max.
Unit
ns
tP
tH
tL
–
–
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
–
ns
Low Time
–
–
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
–
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
–
4
tD
tJC
Measured on rising and falling edge at 1.5V
45
–
–
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
–
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
–
–
–
500
4
ps
ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
–
–
–
3
–
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
30
:
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min.
Typ.
–
Max. Unit
tP
tH
tL
Period
15
5.25
5.05
1
–
–
ns
ns
High Time
–
Low Time
–
–
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
–
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
–
4
tD
tJC
Measured on rising and falling edge at 1.5V
45
–
–
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
–
ps
tSK
fST
Output Skew
Measured on rising edge at 1.5V
–
–
–
–
250
3
ps
FrequencyStabilizationfrom Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
AC Output Impedance
Zo
Average value during switching transition. Used
for determining series termination value.
–
30
–
:
APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated from PCI divided by 2
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
PCI/2
MHz
tR
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
55
3
fST
Frequency Stabilization
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
:
Rev 1.0,November 25, 2006
Page 16 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
