CY28437
Table 3. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Bit
28
29
Description
Acknowledge from slave
Stop
Bit
27:21
28
Slave address – 7 bits
Read
29
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
SRC[T/C]7
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4_SATA
SRC[T/C]3
SRC[T/C]4_SATA Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
DOT96[T/C]
USB_0
DOT96[T/C]MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_0 MHz Output Enable
0 = Disabled, 1 = Enabled
REF
REF Output Enable
0 = Disabled, 1 = Enabled
3
2
0
1
RESERVED
CPU[T/C]1
RESERVED, Set = 0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
1
0
1
0
CPU[T/C]0
CPU
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Rev 1.0,November 20, 2006
Page 5 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
