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CY28437OXC 参数 Datasheet PDF下载

CY28437OXC图片预览
型号: CY28437OXC
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 时钟发生器
文件页数/大小: 22 页 / 195 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28437  
Byte 10: Control Register 10 (continued)  
Bit  
@Pup  
Name  
Description  
0
0
WD_EN  
Watchdog timer enable, when the bit is asserted, Watchdog timer is  
triggered and time stamp of WD_Timer is loaded  
0 = Disable, 1 = Enable  
Byte 11: Control Register 11  
Bit  
@Pup  
Name  
Description  
7
0
CPU_DAF_N7  
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and  
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.  
The setting of the FS_Override bit determines the frequency ratio for CPU  
and other output clocks. When it is cleared, the same frequency ratio  
stated in the Latched FS[E:A] register will be used. When it is set, the  
frequency ratio stated in the FSEL[3:0] register will be used.  
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CPU_DAF_N6  
CPU_DAF_N5  
CPU_DAF_N4  
CPU_DAF_N3  
CPU_DAF_N2  
CPU_DAF_N1  
CPU_DAF_N0  
Byte 12: Control Register 12  
Bit  
@Pup  
Name  
Description  
7
0
CPU_DAF_N8  
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]  
and CPU_FSEL_M[6:0] will be used to determine the CPU output  
frequency.  
The setting of the FS_Override bit determines the frequency ratio for CPU  
and other output clocks. When it is cleared, the same frequency ratio  
stated in the Latched FS[E:A] register will be used. When it is set, the  
frequency ratio stated in the FSEL[3:0] register will be used.  
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CPU_DAF_M6  
CPU_DAF_M5  
CPU_DAF_M4  
CPU_DAF_M3  
CPU_DAF_M2  
CPU_DAF_M1  
CPU_DAF_M0  
Byte 13: Control Register 13  
Bit  
7
@Pup  
Name  
Description  
SRC Dial-A-Frequency Bit N7  
SRC Dial-A-Frequency Bit N6  
SRC Dial-A-Frequency Bit N5  
SRC Dial-A-Frequency Bit N4  
SRC Dial-A-Frequency Bit N3  
SRC Dial-A-Frequency Bit N2  
SRC Dial-A-Frequency Bit N1  
SRC Dial-A-Frequency Bit N0  
0
0
0
0
0
0
0
0
SRC_N7  
SRC_N6  
SRC_N5  
SRC_N4  
SRC_N3  
SRC_N2  
SRC_N1  
SRC_N0  
6
5
4
3
2
1
0
Rev 1.0,November 20, 2006  
Page 9 of 22