PRELIMINARY
CY28437
Clock Generator for Intel£ꢀGrantsdale Chipset
• Dial-A-Frequency£
Features
• Watchdog timer
• Compliant to Intel£ CK410
• Two Independent Overclocking PLLs
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• Low-voltage frequency select input
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
• 33 MHz PCI clock
CPU
x 2
SRC
x 8
PCI
x 8
REF
x 2
DOT96
x 1
USB
x 2
• Dynamic Frequency Control
Block Diagram
Pin Configuration
VDD_RE
F
RE
F
1
2
56
VDD_PCI
VSS_PCI
Xin
PCI2/DF1
PCI1/DF0
14.318MHz
Crystal
Xout
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
4
5
6
7
8
9
DF2/PCI3
*FS_E/PCI4
PCI5
VSS_PCI
VDD_PCI
PCI0/SRESET#
REF1/**FS_C
REF0/**FS_D
VSS_REF
PLL Reference
IREF
VDD_CPU
CPUT
CPUC
CPU
XIN
Divider
PLL
**DF_EN/PCIF0
**SRESET_EN/PCIF1
VTT_PWRGD#/PD
VDD_48
**FS_A/USB48_0
VSS_48
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FS_[E:A]
VDD_SRC
SRCT
SRCC
DOT96T
DOT96C
*FS_B/USB48_1
SRCT0
SRC
Divider
PLL
SRCC0
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
VDD_SRC
VSSA
VDDA
SATA
Divider
PLL
SRCT4_SATA
SRCC4_SATA
SRCT7
SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
VDD_48Mhz
FIX
DOT96T
DOT96C
Divider
PLL
VDD_48
USB48
SRCC5
VSS_SRC
VTTPWR_GD#/PD
VDD_PCI
PCI
* Indicates internal pull-up
DF_EN
VDD_PCI
** Indicates internal pull-down
Dynamic
Frequency
PCIF
DF[2:0]
Watchdog
Timer
I2C
Logic
SDATA
SCLK
SRESET#
Rev 1.0, November 20, 2006
Page 1 of 22
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
SPECTRALINEAR [ SPECTRALINEAR INC ]
