CY28437
Pin Description
Pin No.
Name
VDD_PCI
VSS_PCI
Type
Description
1,7
2,6
4
PWR 3.3V power supply for outputs.
GND Ground for outputs.
FS_E/PCI4
I/O,SE, 3.3V-tolerant input for CPU frequency selection/33-MHz clock.
PU Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
5
8
PCI
O, SE 33 MHz clocks.
DF_EN/PCIF0
I/O, SE 3.3V LVTTL input to Enable DF pin/33-MHz Output.
PD 1 = Enable, 0 = Disable.
Intel Type-5 output buffer
9
SRESET_EN/PCIF I/O,PD, 3.3V LVTTL input to enable Watchdog/33-MHz clocks.
SE 1 = Enable, 0 = Disable
1
10
VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, and FSE inputs. After VTT_PWRGD# (active LOW) assertion, this pin
becomes a real-time input for asserting power-down (active HIGH).
11
12
VDD_48
PWR 3.3V power supply for outputs.
FS_A/USB48_0
I/O,PD, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
SE
13
VSS_48
GND Ground for outputs.
14,15
16
DOT96T, DOT96C O, DIF Fixed 96-MHz clock output.
FS_B/USB48_1 I/O,PU, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
17,18,19,20, SRCT/C
22,23,24,25,
31,30,33,32,
35,36
O, DIF Differential serial reference clocks. Outputs have overclocking capability.
21,28,34
26,27
VDD_SRC
PWR 3.3V power supply for outputs.
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
29
37
38
39
VSS_SRC
VDDA
GND Ground for outputs.
PWR 3.3V power supply for PLL.
GND Ground for PLL.
VSSA
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
42
VDD_CPU
PWR 3.3V power supply for outputs.
O, DIF Differential CPU clock outputs.
GND Ground for outputs.
44,43,41,40 CPUT/C
45
46
47
48
49
50
51
52
VSS_CPU
SCLK
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
SDATA
I/O
VDD_REF
XOUT
PWR 3.3V power supply for outputs.
O, SE 14.318 MHz crystal output.
XIN
I
14.318 MHz crystal input.
VSS_REF
FS_D/REF0
GND Ground for outputs.
I/O,SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
53
FS_C/REF1
PCI0/SRESET#
DF/PCI
I/O,SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications.
54
O
33 MHz clocks/3.3V LVTTL output for Watchdog reset.
PU When configured as SRESET# output this output becomes open drain type with a
high (>100k:) internal pull-up resistor.
I/O, SE 3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output.
3,55,56
Rev 1.0,November 20, 2006
Page 2 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
