CY28372
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
VDD_CPU
ꢀꢁ:
TPCB
Measurement Point
CPUT/C
5pF
VDD_CPU
ꢂꢃ:
TPCB
Measurement Point
CPUCS
5pF
Figure 7. CPUCLK Test Load Configuration
O u tp u t u nd e r T e st
P ro b e
L o a d C a p
3 .3 V s ig n a ls
tD C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0 V
T r
T f
Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)
Table 7. Group Timing Relationship and Tolerances
Offset (Typical)
2 ns
Tolerance (or Range)
1 – 4 ns
Conditions
CPU leads
CPU leads
CPU leads
Notes
CPU to AGP
CPU to Z
–
–
–
2 ns
2 ns
1 – 4 ns
CPU to PCI
1 – 4 ns
Layout Example
Rev 1.0,November 20, 2006
Page 15 of 17
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