CY28372
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup). The
PCIF clocks will not be affected by this pin if their control bits
in the SMBus register are set to allow them to be free running.
CPU_STP#
CPUT
three-state
three-state
CPUC
CPUTint
CPUCint
Figure 4. CPU_STP# Deassertion Waveform
t setup
PCI_STP#
PCIF 33M
PCI 33M
Figure 5. PCI_STP# Assertion Waveform
PCI_STP# - Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
tsetup
PCI_STP#
PCIF
PCI
Figure 6. PCI_STP# Deassertion Waveform
Rev 1.0,November 20, 2006
Page 11 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
