CY28372
PD# – Deassertion
After the clock chip internal PLL is powered up and locked, all
outputs will be enabled within a few clock cycles of each other,
with the first to last active clock taking no more than two full
PCI clock cycles.
1.2 ms
PD#
CPUT
Driven
Driven
CPUC
PCI 33MHz
3V66
USB 48MHz
REF 14.318MHz
Figure 2. Power Down Deassertion Timing Waveforms
Table 6. PD# Functionality
PD#
1
CPUT
Normal
Float
CPUC
Normal
Float
AGP
Normal
Low
PCIF/PCI
Normal
Low
48MHz
Normal
Low
0
CPU_STP# Clarification
CPU_STP#
CPUT
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
three-state
three-state
CPU_STP# – Assertion
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising CPUC clock edges. The final state of the stopped CPU
signals is CPUT = CPUC = three-state.
CPUC
Figure 3. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner. Synchronous manner
meaning that no short or stretched clock pulses will be
produced when the clock resumes. The maximum latency
from the deassertion to active outputs is no more than two
CPUC clock cycles.
Rev 1.0,November 20, 2006
Page 10 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
