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CY28349B 参数 Datasheet PDF下载

CY28349B图片预览
型号: CY28349B
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的Intel㈢ Pentium㈢ 4的CPU和芯片组 [FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets]
分类和应用:
文件页数/大小: 20 页 / 222 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28349B  
Data Byte 2  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
Name  
Pin Description  
Pin Description  
Pin Description  
Reserved  
PCI6  
Reserved  
0
1
1
1
1
1
1
1
17  
16  
15  
14  
12  
11  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
PCI5  
PCI4  
PCI3  
PCI2  
PCI1  
10  
PCI0  
Data Byte 3  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
Name  
8
7
6
PCI_F2  
PCI_F1  
PCI_F0  
Reserved  
(Active/Inactive)  
(Active/Inactive)  
(Active/Inactive)  
Reserved  
1
1
1
0
1
0
1
1
44, 45 CPU_ITP, CPU_ITP#  
(Active/Inactive)  
Reserved  
1
Reserved  
REF1  
(Active/Inactive)  
(Active/Inactive)  
48  
REF0  
Data Byte 4  
Power On  
Default  
Bit  
Pin#  
Name  
Bit 7  
MULTSEL_Override  
This bit control the selection of IREF multiple.  
0 = HW control; IREF multiplier is determined by  
MULTSEL[0:1] input pins  
0
1 = SW control; IREF multiplier is determined by Byte[4],  
Bit[5:6].  
Bit 6  
Bit 5  
SW_MULTSEL1  
SW_MULTSEL0  
IREF multiplier  
0
0
00 = Ioh is 4 x IREF  
01 = Ioh is 5 x IREF  
10 = Ioh is 6 x IREF  
11 = Ioh is 7 x IREF  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Data Byte 5  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Pin#  
10  
7
Name  
Latched FS4 input  
Latched FS3 input  
Latched FS2 input  
Latched FS1 input  
Latched FS0 input  
Pin Description  
Latched FS[4:0] inputs. These bits are read-only.  
X
X
X
X
X
6
23  
22  
Rev 1.0,November 20, 2006  
Page 7 of 20  
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