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CY28349B 参数 Datasheet PDF下载

CY28349B图片预览
型号: CY28349B
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的Intel㈢ Pentium㈢ 4的CPU和芯片组 [FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets]
分类和应用:
文件页数/大小: 20 页 / 222 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28349B的Datasheet PDF文件第7页浏览型号CY28349B的Datasheet PDF文件第8页浏览型号CY28349B的Datasheet PDF文件第9页浏览型号CY28349B的Datasheet PDF文件第10页浏览型号CY28349B的Datasheet PDF文件第12页浏览型号CY28349B的Datasheet PDF文件第13页浏览型号CY28349B的Datasheet PDF文件第14页浏览型号CY28349B的Datasheet PDF文件第15页  
CY28349B  
Data Byte 13  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
Name  
CPU_FSEL_N7  
Pin Description  
If Prog_Freq_EN is set, the values programmed in  
0
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to  
determine the CPU output frequency. The new frequency  
will start to load whenever CPU_FSELM[6:0] is updated.  
The setting of FS_Override bit determines the frequency  
ratio for CPU and other output clocks. When it is cleared,  
the same frequency ratio stated in the Latched FS[4:0]  
register will be used. When it is set, the frequency ratio  
stated in the SEL[4:0] register will be used.  
CPU_FSEL_N6  
CPU_FSEL_N5  
CPU_FSEL_N4  
CPU_FSEL_N3  
CPU_FSEL_N2  
CPU_FSEL_N1  
CPU_FSEL_N0  
0
0
0
0
0
0
0
Data Byte 14  
Power On  
Default  
Bit  
Pin#  
Name  
Pin Description  
Bit 7  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled  
1 = Enabled  
0
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
CPU_FSEL_M6  
CPU_FSEL_M5  
CPU_FSEL_M4  
CPU_FSEL_M3  
CPU_FSEL_M2  
CPU_FSEL_M1  
CPU_FSEL_M0  
If Prog_Freq_EN is set, the values programmed in  
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to  
determine the CPU output frequency. The new frequency  
will start to load whenever CPU_FSELM[6:0] is updated.  
The setting of FS_Override bit determines the frequency  
ratio for CPU and other output clocks. When it is cleared,  
the same frequency ratio stated in the Latched FS[4:0]  
register will be used. When it is set, the frequency ratio  
stated in the SEL[4:0] register will be used.  
0
0
0
0
0
0
0
Data Byte 15  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
Name  
Pin Description  
Reserved  
Reserved  
0
0
0
0
0
0
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Vendor Test Mode  
Vendor Test Mode  
Reserved. Write with “1”  
Reserved. Write with “1”  
Data Byte 16  
Power On  
Default  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin#  
Name  
Reserved  
Pin Description  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Rev 1.0,November 20, 2006  
Page 11 of 20  
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