欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY28349B 参数 Datasheet PDF下载

CY28349B图片预览
型号: CY28349B
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的Intel㈢ Pentium㈢ 4的CPU和芯片组 [FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets]
分类和应用:
文件页数/大小: 20 页 / 222 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28349B的Datasheet PDF文件第9页浏览型号CY28349B的Datasheet PDF文件第10页浏览型号CY28349B的Datasheet PDF文件第11页浏览型号CY28349B的Datasheet PDF文件第12页浏览型号CY28349B的Datasheet PDF文件第14页浏览型号CY28349B的Datasheet PDF文件第15页浏览型号CY28349B的Datasheet PDF文件第16页浏览型号CY28349B的Datasheet PDF文件第17页  
CY28349B  
Table 4. Frequency Selection Table (continued)  
Input Conditions  
Output Frequency  
PLL Gear  
Constants  
(G)  
FS4  
SEL4  
1
FS3  
SEL3  
1
FS2  
SEL2  
1
FS1  
SEL1  
1
FS0  
SEL0  
1
CPU  
3V66  
PCI  
133.3  
66.6  
33.3  
48.00741  
The Watchdog Timer and Recovery Output Frequency  
features allow users to implement a recovery mechanism  
when the system hangs or gets unstable. System BIOS or  
other control software can enable the Watchdog Timer before  
they attempt to make a frequency change. If the system hangs  
and a Watchdog Timer time-out occurs, a system reset will be  
generated and a recovery frequency will be activated.  
Programmable Output Frequency, Watchdog  
Timer and Recovery Output Frequency  
Functional Description  
The Programmable Output Frequency feature allows users to  
generate any CPU output frequency from the range of 50 MHz  
to 248 MHz. Cypress offers the most dynamic and the simplest  
programming interface for system developers to utilize this  
feature in their platforms.  
All of the related registers are summarized in Table 5.  
Table 5. Register Summary  
Name  
Description  
Pro_Freq_EN  
Programmable output frequencies enabled  
0 = Disabled (default)  
1 = Enabled.  
When it is disabled, the operating output frequency will be determined by either the latched value of  
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs  
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.  
When it is enabled, the CPU output frequency will be determined by the programmed value of  
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]  
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between  
CPU and other frequency outputs.  
FS_Override  
When Pro_Freq_EN is cleared or disabled,  
0 = Select operating frequency by FS input pins (default)  
1 = Select operating frequency by SEL bits in SMBus control bytes.  
When Pro_Freq_EN is set or enabled,  
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the latched value of FS input pins (default)  
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are  
based on the programmed value of SEL bits in SMBus control bytes.  
CPU_FSEL_N,  
CPU_FSEL_M  
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and  
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load  
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-  
mended to use Word or Block write to update both registers within the same SMBus bus operation.  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When  
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.  
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in  
SMBus control bytes.  
ROCV_FREQ_SEL  
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out  
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the  
selection on ROCV_FREQ_SEL.  
0 = From latched FS[4:0]  
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0].  
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a  
Watchdog Timer time-out occurs  
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared,  
the same frequency ratio stated in the Latched FS[4:0] register will be used.  
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.  
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and  
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both  
registers within the same SMBus bus operation.  
WD_EN  
0 = Stop and reload Watchdog Timer  
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.  
Rev 1.0,November 20, 2006  
Page 13 of 20  
 复制成功!