CY28349B
-
Switching Characteristics Over the Operating Range[3]
Parameter
t1
Output
Description
Output Duty Cycle[4]
Rise Time
Test Conditions
Min.
45
Max.
55
Unit
%
All
t1A/(t1B)
t2
t2
t2
t3
t3
t3
t4
t5
t6
t7
t8
CPU
Measured at 20% to 80% of Voh
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Measured at 80% to 20% of Voh
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at Crossover
Measured at 1.5V
175
0.5
1.0
175
0.5
1.0
700
2.0
ps
48MHz, REF
PCI, 3V66,
CPU
Rising Edge Rate
Rising Edge Rate
Fall Time
V/ns
V/ns
ps
4.0
700
2.0
48MHz, REF
PCI, 3V66
CPU
Falling Edge Rate
Falling Edge Rate
CPU-CPU Skew
3V66-3V66 Skew
PCI-PCI Skew
V/ns
V/ns
ps
4.0
150
500
500
3.5
3V66 [0:1]
PCI
ps
Measured at 1.5V
ps
3V66,PCI
CPU
3V66-PCI Clock Skew
Cycle-Cycle Clock Jitter
3V66 leads. Measured at 1.5V
1.5
ns
Measured at Crossover t8 = 8A
t
– t8B
200
ps
With all outputs running
t9
t9
t9
t9
3V66
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Settle Time
Measured at 1.5V t9 = 9A
Measured at 1.5V t9 = 9A
Measured at 1.5V t9 = 9A
Measured at 1.5V t9 = 9A
t
– t9B
– t9B
– t9B
– t9B
250
350
500
1000
3
ps
ps
ps
ps
ms
48MHz
PCI
t
t
REF
t
CPU, PCI
CPU and PCI clock stabilization from
power-up
CPU
CPU
Rise/Fall Matching
Overshoot
Measured with test loads[5, 6]
Measured with test loads[6]
20%
Voh
+
V
0.2
CPU
CPU
CPU
CPU
Undershoot
Measured with test loads[6]
Measured with test loads[6]
Measured with test loads[6]
Measured with test loads[6]
–0.2
0.65
0.0
V
V
V
V
Voh
High-level Output Voltage
Low-level Output Voltage
Crossover Voltage
0.74
0.05
Vol
Vcrossover
45%of 55% of
0.65 0.74
Notes:
3. All parameters specified with loaded outputs.
4. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V.
5. Determined as a fraction of 2*(Trp – Trn)/(Trp + Trn) Where Trp is a rising edge and Trn is an intersecting falling edge.
DD
DD
6. The test load is R = 33.2:, R = 49.9: in test circuit.
s
p
Rev 1.0,November 20, 2006
Page 16 of 20