CY28347
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Off
Figure 17. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SELP4_K7# = 1)[26]
S 1
S 2
W ait for
1.14 6m s
S am ple
Inpu ts
F S (3:0)
E n able
O utp utes
D elay 0.25 m S
V D D A = 2.0V
S 0
S 3
N orm al
O peration
P o w e r O ff
V D D 3.3 = O ff
Figure 18. Clock Generator Power-up/Run State Diagram (with P4 Processor SELP4_K7# = 1)
Ordering Information
Part Number
CY28347OC
Package Type
Product Flow
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
56-pin Shrunk Small Outline Package (SSOP)
CY28347OCT
CY28347ZC
CY28347ZCT
56-pin Shrunk Small Outline Package (SSOP) – Tape and Reel
56-pin Thin Shrunk Small Outline package (TSSOP)
56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel
Note:
26. This timing diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power up. After the first HIGH to LOW transition of VTT_PWRGD#,
device is not affected, VTT_PWRGD# is ignored.
Rev 1.0,November 20, 2006
Page 20 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
