CY28347
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the CPU. When PD# is sampled LOW by two consecutive
rising edges of the CPUCS_C clock, then all affected clocks
are stopped in a LOW state after the next HIGH to LOW
transition or remains LOW. When in power-down (and before
power is removed), all outputs are synchronously stopped in a
LOW state (see Figure 15 below), all PLLs are shut off, and
the crystal oscillator is disabled. When the device is shutdown,
the I2C function is also disabled.
PWRDWN#
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
Figure 15. Power-down Assertion Timing Waveform (in K7 Mode)
Power Down Deassertion (K7 Mode)
When deasserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
order to guarantee a glitch-free operation, no partial clock
pulses.
<1.5 msec
PWRDWN#
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
Figure 16. Power-down Deassertion Timing Waveform (in K7 Mode)
Rev 1.0,November 20, 2006
Page 19 of 21
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