CY28347
For Open Drain CPU Output Signals
(with K7 Processor SELP4_K7# = 0)
3.3V
60.4 Ohm
VDDCPU(1.5V)
500 Ohm
Measurement Point
47 Ohm
52ꢀOhmꢀꢀ5"
52ꢀOhmꢀꢀꢁ"
CPUOD_T
680 pF
20 pF
500 Ohm
301 Ohm
VDDCPU(1.5V)
52ꢀOhmꢀꢀ1"
47 Ohm
52ꢀOhmꢀꢀ5"
500 Ohm
CPUOD_C
Measurement Point
680 pF
60.4 Ohm
20 pF
500 Ohm
3.3V
Figure 2. K7 Termination
6”
6”
Figure 3. Chipset Termination
For Differential CPU Output Signals (with P4 Processor SELP4_K7#= 1)
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs. Figure 4 is for the 1.0V
amplitude signalling and Figure 5 is for the 0.7V amplitude
signalling.
TPCB
33.2:
Measurement Point
CPUT
2 pF
475:
33.2:
MULTSEL
TPCB
Measurement Point
CPUC
2 pF
63.4:
63.4:
IREF
221:
Figure 4. P4 1.0V Configuration
Rev 1.0,November 20, 2006
Page 13 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
