CY28347
CPU_STP# Assertion (K7 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by two rising CPUC clock edges.
The final state of the stopped CPU signal is CPUOD_T = LOW
and CPUOD_C = LOW.
CPU_STP#
CPUOD_T
CPUOD_C
Figure 9. CPU_STP# Assertion Waveform (K7 Mode)
CPU_STP# Deassertion (K7 Mode)
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUOD_T
CPUOD_C
CPUCS_T
CPUCS_C
Figure 10. CPU_STP# Deassertion Waveform (K7 Mode)
Rev 1.0,November 20, 2006
Page 16 of 21
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