CY28325-3
AC Electrical Specifications[3] (continued)
Parameter
t9
0.7V CPUT/C, CPU_CS
Output
Description
Test Conditions
Measured at 1.5V t9 = 9A – t9B
Min.
Max.
Unit
REF
Cycle-Cycle Clock Jitter
t
–
1000
ps
t2
CPU
Rise Time
Fall Time
Measured single ended waveform from 0.175
0.175V to 0.525V
1.6
1.6
ns
ns
t3
CPU
Measured single ended waveform from 0.175
0.525V to 0.175V
t4
t8
CPU
CPU
CPU-CPU Skew
Measured at Crossover
–
–
150
300
ps
ps
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = 8A
t
– t8B
With all outputs running
Measured with test loads[5, 6]
Measured with test loads[6]
CPU
CPU
Rise/Fall Matching
–
–
20
%
V
Voh
High-level Output Voltage
including overshoot
0.85
Vol
CPU
CPU
Low-level Output Voltage
including undershoot
Measured with test loads[6]
Measured with test loads[6]
–0.15
0.28
–
V
V
Vcrossover
Crossover Voltage
0.43
Switching Waveforms
(Single-ended Output)
Duty Cycle Timing
t1B
t1A
(CPU Differential Output)
Duty Cycle Timing
t1B
t1A
All Outputs Rise/Fall Time
VDD
0V
OUTPUT
t2
t3
Notes:
3. All parameters specified with loaded outputs.
4. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measure at 1.25V.
DD
DD
5. Determined as a fraction of 2*(Trp-Trn)(TRP+Trn) where Trp is a rising edge and Trp is an intersectiong falling edge.
6. The 0.7V test load is R =33.2ohm, R = 49.9ohm in test circuit.
7. Characterize with control register, data byte 9, bits 5 and 6 = 1.
S
P
Rev 1.0,November 21, 2006
Page 16 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
