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CY28325OC-3T 参数 Datasheet PDF下载

CY28325OC-3T图片预览
型号: CY28325OC-3T
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™奔腾4 ™芯片组 [FTG for VIA⑩ Pentium 4⑩ Chipsets]
分类和应用:
文件页数/大小: 18 页 / 206 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28325OC-3T的Datasheet PDF文件第6页浏览型号CY28325OC-3T的Datasheet PDF文件第7页浏览型号CY28325OC-3T的Datasheet PDF文件第8页浏览型号CY28325OC-3T的Datasheet PDF文件第9页浏览型号CY28325OC-3T的Datasheet PDF文件第11页浏览型号CY28325OC-3T的Datasheet PDF文件第12页浏览型号CY28325OC-3T的Datasheet PDF文件第13页浏览型号CY28325OC-3T的Datasheet PDF文件第14页  
CY28325-3  
Data Byte 9 (continued)  
Power-on  
Default  
Bit  
Pin#  
Name  
Pin Description  
2
WD_TO_STAT Watchdog Timer Time-out Status Bit  
US  
0
0 = No time-out occurs (Read); Ignore (Write)  
1 = time-out occurred (Read); Clear WD_TO_STATUS (Write)  
1
WD_EN  
0 = Stop and re-load Watchdog timer  
1 = Enable Watchdog timer. It will start counting down after a frequency  
change occurs.  
0
Note:CY28325-3 will generate system reset, re-load a recovery frequency,  
and lock itself into a recovery frequency mode after a Watchdog timer  
time-out occurs. Under recovery frequency mode, CY28325-2 will not  
respond to any attempt to change the output frequency via the SMBus  
control bytes. System software can unlock the CY28325-3 from its recovery  
frequency mode by clearing the WD_EN bit.  
0
Reserved  
Reserved  
0
Data Byte 10  
Power-on  
Default  
Bit  
7
Pin#  
Name  
Pin Description  
CPU_CS_F Skew Control  
CPU_CS_F Skew2  
CPU_CS_F Skew1  
CPU_CS_F Skew0  
0
0
0
000 = Normal  
001 = –150 ps  
010 = –300 ps  
011 = –450 ps  
100 = +150 ps  
101 = +300 ps  
110 = +450 ps  
111 = +600 ps  
6
5
4
3
2
CPU_Skew2  
CPU_Skew1  
CPU_Skew0  
CPUT_0:1 and CPUC_0:1 Skew Control  
000 = Normal  
001 = –150 ps  
010 = –300 ps  
011 = –450 ps  
0
0
0
100 = +150 ps  
101 = +300 ps  
110 = +450 ps  
111 = +600 ps  
1
0
AGP_Skew1  
AGP_Skew0  
AGP Skew control  
00 = Normal  
01 = –150 ps  
10 = +150 ps  
11 = +300 ps  
0
0
Data Byte 11  
Power-on  
Default  
Bit  
7
Pin#  
Name  
Pin Description  
ROCV_FREQ_N7  
ROCV_FREQ_N6  
ROCV_FREQ_N5  
ROCV_FREQ_N4  
ROCV_FREQ_N3  
ROCV_FREQ_N2  
ROCV_FREQ_N1  
ROCV_FREQ_N0  
If ROCV_FREQ_SEL is set, the values programmed in  
0
0
0
0
0
0
0
0
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to  
determine the recovery CPU output frequency when a Watchdog Timer  
time-out occurs. The setting of FS_Override bit determines the frequency  
ratio for CPU and other output clocks. When FS_Override bit is cleared,  
the same frequency ratio stated in the Latched FS[4:0] register will be  
used. When it is set, the frequency ratio stated in the SEL[4:0] register  
will be used.  
6
5
4
3
2
1
0
Rev 1.0,November 21, 2006  
Page 10 of 18  
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