CY28316
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
48.008
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz × 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V
Assumes full supply voltage reached within 1 ms
55
3
fST
Frequency Stabilization
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
:
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 24 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(24.004 – 24)/24
Min.
Typ.
24.004
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz × 57/34 = 24.004 MHz)
Measured from 0.4V to 2.4V
57/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
:
Rev 1.0,November 20, 2006
Page 15 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
