CY28316
AC Electrical Characteristics (TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, fXTL = 14.31818 MHz)
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[8]
CPU = 100 MHz
CPU = 133 MHz
Parameter
tR
Description
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
1.0
1.0
45
4.0
4.0
55
1.0
1.0
45
4.0 V/ns
4.0 V/ns
tF
tD
Measured at 50% point
55
%
ps
tJC
fST
Jitter, Cycle to Cycle
375
375
Frequency Stabilization Assumes full supply voltage reached
3
3
ms
from Power-up (cold
start)
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance VO = VX
50
50
:
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
tP Measured on the rising edge at 1.5V
Min. Typ. Max. Unit
Period
30
12
12
1
ns
ns
tH
tL
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on the rising and falling edges at 1.5V
45
55
Jitter, Cycle-to-Cycle
Measured on the rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
250 ps
tSK
tO
Output Skew
Measured on the rising edge at 1.5V
500 ps
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on the rising edge at 1.5
1.5V. CPU leads PCI output.
4
3
ns
ms
:
fST
Zo
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold start) power-up. Short cycles exist prior to frequency stabilization.
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
30
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by the crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
MHz
tR
0.5
0.5
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on the rising and falling edges at 1.5V 45
55
3
fST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
ms
Power-up (cold start)
AC Output Impedance
Zo
Average value during switching transition. Used
for determining series termination value.
40
:
Note:
8. Refer to Figure 1 for K7 operation clock driver test circuit.
Rev 1.0,November 20, 2006
Page 14 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
