CY28316
Byte 17: Reserved Register (continued)
Bit
Pin#
Name
Reserved
Default
Description
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
-
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved
Reserved
Reserved
Reserved
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
FS4
SEL4
0
FS3
SEL3
0
FS2
SEL2
0
FS1
SEL1
0
FS0
SEL0
0
PLL Gear
Constant (G)
CPU
200.0
190.0
180.0
170.0
166.0
160.0
150.0
145.0
140.0
136.0
130.0
124.0
67.2
PCI
33.3
38.0
36.0
34.0
33.2
32.0
37.5
36.3
35.0
34.0
32.5
31.0
33.6
33.6
39.3
33.6
33.5
33.5
38.3
33.5
33.4
33.4
36.7
33.4
35.0
30.0
28.3
39.0
33.3
33.3
37.5
33.3
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
48.000741
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
100.8
118.0
134.4
67.0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
100.5
115.0
134.0
66.8
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
100.2
110.0
133.6
105.0
90.0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
85.0
1
1
0
1
1
78.0
1
1
1
0
0
66.6
1
1
1
0
1
100.0
75.0
1
1
1
1
0
1
1
1
1
1
133.3
Rev 1.0,November 20, 2006
Page 10 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
