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CY28316PVCT 参数 Datasheet PDF下载

CY28316PVCT图片预览
型号: CY28316PVCT
PDF下载: 下载PDF文件 查看货源
内容描述: FTG威盛PL133T和PLE133T [FTG for VIA PL133T and PLE133T]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 17 页 / 207 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28316  
Byte 7: Control Register 7  
Bit  
Bit 7  
Pin#  
Name  
Reserved  
Default  
Pin Description  
0
1
1
0
0
0
0
0
Reserved.  
Bit 6  
25  
26  
24_48MHz_DRV  
48MHz_DRV  
Reserved  
0 = Norm, 1 = High Drive.  
0 = Norm, 1 = High Drive.  
Reserved.  
Bit 5  
Bit 4  
Bit 3  
Reserved  
Reserved.  
Bit 2  
Reserved  
Reserved.  
Bit 1  
Reserved  
Reserved.  
Bit 0  
Reserved  
Reserved.  
Byte 8: Vendor ID and Revision ID Register (Read Only)  
Bit  
Name  
Revision_ID3  
Revision_ID2  
Revision_ID1  
Revision_ID0  
Vendor_ID3  
Vendor_ID2  
Vendor _ID1  
Vendor _ID0  
Default  
Pin Description  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
1
0
0
0
Revision ID bit[3].  
Revision ID bit[2].  
Revision ID bit[1].  
Revision ID bit[0].  
Bit[3] of Cypress’s Vendor ID. This bit is read-only.  
Bit[2] of Cypress’s Vendor ID. This bit is read-only.  
Bit[1] of Cypress’s Vendor ID. This bit is read-only.  
Bit[0] of Cypress’s Vendor ID. This bit is read-only.  
Byte 9: System RESET and Watchdog Timer Register  
Bit  
Name  
Default  
Pin Description  
SDRAM clock output drive strength.  
0 = Normal.  
Bit 7  
Bit 6  
SDRAM_DRV  
0
1 = High Drive.  
PCI_DRV  
0
PCI clock output drive strength.  
0 = Normal.  
1 = High Drive.  
Bit 5  
Bit 4  
Reserved  
0
0
Reserved  
RST_EN_WD  
This bit will enable the generation of a Reset pulse when a Watchdog Timer  
time-out occurs.  
0 = Disabled.  
1 = Enabled.  
Bit 3  
RST_EN_FC  
0
This bit will enable the generation of a Reset pulse after a frequency change  
occurs.  
0 = Disabled.  
1 = Enabled.  
Bit 2  
Bit 1  
WD_TO_STATUS  
WD_EN  
0
0
Watchdog Timer Time-out Status bit.  
0 = No time-out occurs (Read); Ignore (Write).  
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write).  
0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency  
mode.  
1 = Enable Watchdog Timer. It will start counting down after a frequency change  
occurs.  
Note: CY28316 will generate a system Reset, reload a recovery frequency, and  
lock itself into a recovery frequency mode after a Watchdog Timer time-out  
occurs. Under recovery frequency mode, CY28316 will not respond to any  
attempt to change output frequency via the SMBus control bytes. System  
software can unlock CY28316 from its recovery frequency mode by clearing the  
WD_EN bit.  
Rev 1.0,November 20, 2006  
Page 7 of 17