D a t a S h e e t ( P r e l i m i n a r y )
6.23 Cache Timing
Figure 6.28 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined for
Read
CMD
31h
Cycle Type
Dout
Dn
Dout
D0
CMD
Dout
D0
Dout
...
CMD
31h
30h
I/Ox
tWB
tWB
tWB
tRR
tRR
tCBSYR
tR
tCBSYR
SR[6]
Figure 6.29 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined
for Read
A
ADDR ADDR ADDR
Dout
Dout
CMD
ADDR
Dout
CMD
00h
CMD
ADDR
C1
Cycle Type
Page N
C2
R1
R2
D0
. . .
30h
R3
Dn
31h
I/Ox
tRR
tR
tRR
tWB
tWB
SR[6]
tCBSYR
A
ADDR ADDR ADDR
Dout
CMD
ADDR
CMD
ADDR
C1
Cycle Type
Page R
C2
R1
R2
D0
00h
R3
31h
I/Ox
tRR
tCBSYR
tWB
SR[6]
Figure 6.30 Read Cache Timing, End Of Cache Operation
As defined for
Read Cache
(Sequential or Random)
Dout
CMD
Dout
CMD
Dout
Dout
Dout
Dout
Cycle Type
Dn
3Fh
31h
D0
D0
. . .
. . .
Dn
I/Ox
tRR
tRR
tCBSYR
tWB
tWB
tCBSYR
SR[6]
56
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
SPANSION [ SPANSION ]
