Da ta
Shee t
(Prelimi nar y)
6.21
Reset Operation Timing
Figure 6.26
Reset Operation Timing
WE#
ALE
CLE
RE#
I/O7:0
FF
t RST
R/B#
6.22
Read Cache Operation Timing
Figure 6.27
Read Cache Operation Timing
A
CE#
CLE
ALE
WE#
RE#
I/Ox
00h
Col.
Add 1
Col.
Add 2
Row
Add 1
Row
Add 2
Row
Add
3
30h
31h
tWC
tWB
tWB
tRC
tRR
Dout
0
Dout
1
Dout
31h
tWB
tRC
tRR
Dout
0
Dout
1
Column Address 00h
R/B#
Page Address M
tR
tCBSYR
Col. Add. 0
Page Address M
tCBSYR
Page Address M + 1
Col. Add. 0
1
2
A
CE#
CLE
ALE
3
WE#
RE#
tWB
tRC
tRR
tWB
tRC
tRR
tWB
tRC
tRR
I/Ox
Dout
31h
Dout
0
Dout
1
Dout
31h
Dout
0
Dout
1
Dout
3Fh
Dout
0
Dout
1
Page Address M + 2
Col. Add. 0
R/B#
tCBSYR
tCBSYR
Page Address M +
3
Col. Add. 0
tCBSYR
Page Address M + 4
Col. Add. 0
4
5
6
7
8
: Don’t Care
9
Data Cache
1
Page Buffer
2
3
Page N
4
5
Page N + 1
6
7
Page N
8
9
Page N +
3
Page N
1
3
Page N + 1
5
Page N + 2
7
Page N +
3
Cell Array
Page N
Page N + 1
Page N + 2
Page N +
3
September 6, 2012 S34ML01G1_04G1_10
Spansion
®
SLC NAND Flash Memory for Embedded
55
SPANSION [ SPANSION ]
