Da ta
Shee t
(Prelimi nar y)
Figure 6.21
Multiplane Copy Back Program (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
SR[6]
85h
C1
C
C2
C
R1
C
R2
C
R3
C
11h
t IPBSY
85h
C1
D
C2
D
R1
D
R2
D
R3
D
10h
t PROG
A
Notes:
1. C1C-C2C Column address for page C. C1A is the least significant byte.
2. R1C-R3C Row address for page C. R1A is the least significant byte.
3. D0C-DnC Data to program for page C.
4. C1D-C2D Column address for page D. C1B is the least significant byte.
5. R1D-R3D Row address for page D. R1B is the least significant byte.
6. D0D-DnD Data to program for page D.
7. Same restrictions on address of pages C and D, and allowed commands as
apply.
6.19
Read Status Cycle Timing
Figure 6.22
Status / EDC Read Cycle
t
CLR
CLE
tCLS
t
CLH
t
CS
CE#
t
CH
t
WP
WE#
t
WHR
t
CEA
t
CHZ
t
COH
RE#
t
RHZ
t
DS
t
DH
t
IR
t
REA
t
RHOH
Status
Output
I/Ox
70h or 7Bh
(Note 1)
Note:
1. Extended Status Read commands F2h, F3h, F4h, and F5h are also valid for multi-die stacks.
September 6, 2012 S34ML01G1_04G1_10
Spansion
®
SLC NAND Flash Memory for Embedded
53
SPANSION [ SPANSION ]
