P R E L I M I N A R Y
Table 23. Write Operation Status ......................................... 81
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .82
Figure 8. Maximum Overshoot Waveforms............................. 82
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .83
Industrial (I) Devices ..........................................................................................83
Extended (E) Devices .........................................................................................83
Supply Voltages ....................................................................................................83
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 24. CMOS Compatible ................................................ 84
AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .85
Test Conditions .................................................................................................. 85
Figure 9. Test Setups......................................................... 85
Table 25. Test Specifications ............................................... 85
SWITCHING WAVEFORMS .........................................................................86
Table 26. KEY TO SWITCHING WAVEFORMS ......................... 86
Figure 10. Input Waveforms and Measurement Levels............. 86
VCC RampRate ..................................................................................................86
Figure 18. Data# Polling Timings (During Embedded Algorithms)..
........................................................................................ 93
Figure 19. Toggle Bit Timings (During Embedded Algorithms).. 93
Figure 20. DQ2 vs. DQ6 ..................................................... 94
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 30. Temporary Sector Unprotect ................................. 94
Figure 21. Temporary Sector Unprotect Timing Diagram......... 94
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram........................................................................... 95
Controlled Erase Operations .........................................................................96
Table 31. Alternate CE# Controlled Erase and Program Operations
........................................................................................ 96
Table 32. Alternate CE# Controlled Write (Erase/Program) Opera-
tion Timings ...................................................................... 97
Table 33. CE1#/CE2# Timing (S29PL129J only) .................... 97
Figure 23. Timing Diagramfor Alternating Between CE1# and CE2#
Control............................................................................. 98
Table 34. Erase And Programming Performance ..................... 98
Read Operations ................................................................................................ 87
Table 27. Read-Only Operations .......................................... 87
Figure 11. Read Operation Timings....................................... 88
Figure 12. Page Read Operation Timings ............................... 88
Reset ......................................................................................................................89
Table 28. Hardware Reset (RESET#) .................................... 89
Figure 13. Reset Timings..................................................... 89
Erase/Program Operations .............................................................................90
Table 29. Erase and Program Operations .............................. 90
Timing Diagrams .................................................................................................. 91
Figure 14. Program Operation Timings.................................. 91
Figure 15. Accelerated Program Timing Diagram .................... 91
Figure 16. Chip/Sector Erase Operation Timings..................... 92
Figure 17. Back-to-back Read/Write Cycle Timings ................. 92
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 98
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 99
VBG080—80-Ball Fine-pitch Ball Grid Array 8 x 11 mm Package (PL127J
and PL129J) ............................................................................................................99
VBH064—64-Ball Fine-pitch Ball Grid Array 8 x 11.6 mm package
(PL127J) ............................................................................................................... 100
VBK048—48-Ball Fine-pitch Ball Grid Array 8.15 x 6.15 mm package
(PL127J) .................................................................................................................101
TLC056—56-Ball Fine-pitch BGA 7 x 9mm package (PL064J and PL032J)
..................................................................................................................................102
TS056—20 x 14 mm, 56-pin TSOP (PL127J) .............................................103
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 104
April 7, 2005 31107A62
S29PL127J/S29PL129J/S29PL064J/S29PL032J
7
SPANSION [ SPANSION ]
