S29PL127J/S29PL129J/S29PL064J/S29PL032J
128/128/64/32 Megabit (8/8/4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIOTM Control
PRELIMINARY
Distinctive Characteristics
Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the VIO pin
ARCHITECTURAL ADVANTAGES
128/128/64/32 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
— VIO options at 1.8 V and 3 V I/O for PL127J and
PL129J devices
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
— 3V VIO for PL064J and PL032J devices
SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Up to 64 factory-locked words
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
FlexBank Architecture (PL127J/PL064J/PL032J)
— 4 separate banks, with up to two simultaneous
operations per device
Cycling Endurance: 1 million cycles per sector
typical
— Bank A:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
— Bank B:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— Bank C:
PL127J - 48 Mbit (32 Kw x 96)
PL064J - 24 Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
— 0.2 µA typical standby mode current
SOFTWARE FEATURES
— Bank D:
PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
FlexBank Architecture (PL129J)
— 4 separate banks, with up to two simultaneous
operations per device
— CE#1 controlled banks:
Bank 1A:
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
PL129J - 48Mbit (32Kw x 96)
— CE#2 controlled banks:
Bank 2A:
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
PL129J - 48 Mbit (32Kw x 96)
Bank 2B:
PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
Publication Number 31107 Revision A Amendment 62 Issue Date April 7, 2005
SPANSION [ SPANSION ]
