A d v a n c e I n f o r m a t i o n
Hardware Reset (RESET#) .............................................................................. 92
Figure 13. Reset Timings..................................................... 92
Erase and Program Operations–S29GL512N Only ...................................93
Alternate CE# Controlled Erase and Program Operations–
S29GL256N Only ................................................................................................101
Alternate CE# Controlled Erase and Program Operations–
Erase and Program Operations–S29GL256N Only ................................. 94
Erase and Program Operations–S29GL128N Only ...................................95
Figure 14. Program Operation Timings .................................. 96
Figure 15. Accelerated Program Timing Diagram .................... 96
Figure 16. Chip/Sector Erase Operation Timings..................... 97
Figure 17. Data# Polling Timings
(During Embedded Algorithms)............................................ 98
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 99
Figure 19. DQ2 vs. DQ6 ...................................................... 99
Alternate CE# Controlled Erase and Program Operations–
S29GL128N Only ...............................................................................................102
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings............................................................ 103
Erase And Programming Performance . . . . . . . 104
TSOP Pin and BGA Package Capacitance . . . . 104
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . .105
TS056—56-Pin Standard Thin Small Outline Package (TSOP) ............105
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ..............................106
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 107
S29GL512N Only ...............................................................................................100
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
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