A d v a n c e I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
V
V
CC
Sector Switches
SS
V
IO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A
**–A0
Max
** A
GL512N = A24, A
GL256N = A23, A GL128N = A22
Max
Max
Max
May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
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