D a t a S h e e t
Erase And Programming Performance
Typ
Max
Parameter
(Note 1)
(Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
256
sec
Excludes 00h
programming prior to
erasure (Note 5)
S29GL128N
S29GL256N
S29GL512N
64
Chip Erase Time
128
256
512
sec
1024
Total Write Buffer
Programming Time
(Note 3)
240
200
µs
µs
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
Excludes system level
overhead (Note 6)
S29GL128N
S29GL256N
S29GL512N
123
246
492
Chip Program Time
(Note 4)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 10,000 cycles, checkerboard
CC
pattern.
2. Under worst case conditions of 90°C, V = 3.0 V, 100,000 cycles.
CC
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 on page 63 and Table 14 on page 65 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Te st S e tup
Typ
6
Max
7.5
5.0
12
Unit
pF
TSOP
BGA
CIN
Input Capacitance
VIN = 0
4.2
8.5
5.4
7.5
3.9
pF
TSOP
BGA
pF
COUT
Output Capacitance
VOUT = 0
VIN = 0
6.5
9
pF
TSOP
BGA
pF
CIN2
Control Pin Capacitance
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
87
SPANSION [ SPANSION ]
