D a t a S h e e t
Table 15. Sector Protection Commands (x8)
Bus Cycles (Notes 1–4)
1st/8th
2nd/9th
3rd/10th
4th/11th
5th
6th
7th
Command Sequence
(Notes)
Addr
Data
AA
Addr
555
XXX
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
3
2
1
2
3
2
AAA
XXX
00
XXX
AAA
XXX
00
AAA
40
Lock
Register
Bits
Program (6)
A0
Data
Read (6)
Data
90
Command Set Exit (7)
Command Set Entry (5)
Program (8)
XXX
555
00
55
AA
AAA
02
60
A0
PWAx
01
PWDx
PWD1
PWD0
PWD7
25
PWD2
03
PWD3
04
02
PWD4
PWD2
05
03
PWD5
PWD3
06
04
PWD6
PWD4
Read (9)
8
Password
Protection
07
00
00
06
03
PWD6
00
00
07
PWD0
PWD7
01
00
PWD1
29
Unlock (10)
11
05
PWD5
90
Command Set Exit (7)
Command Set Entry (5)
PPB Program (11)
2
3
2
2
1
2
3
2
1
XX
XX
555
SA
00
AAA
XXX
XXX
SA
XXX
AAA
XXX
XXX
AA
A0
55
00
AAA
C0
Non-Volatile
Sector
Protection (PPB)
All PPB Erase (11, 12)
PPB Status Read
80
30
RD(0)
90
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XXX
555
XXX
00
55
00
Global
Volatile Sector
Protection
Freeze
AA
AAA
AAA
50
E0
A0
RD(0)
PPB Lock Bit Status Read
Command Set Exit (7)
2
XXX
90
XX
00
(PPB Lock)
Command Set Entry (5)
DYB Set
DYB Clear
3
2
2
1
2
AAA
XXX
XXX
SA
AA
A0
A0
555
SA
SA
55
00
01
Volatile Sector
Protection
(DYB)
DYB Status Read
Command Set Exit (7)
RD(0)
90
XXX
XXX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If
unprotected, DQ0 = 1.
SA = Sector Address. Any address that falls within a specified sector.
See Tables 2–4 for sector address ranges.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
6. No unlock or command cycles required when bank is reading
array data.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. Password may be unlocked or read in any order. Unlocking
requires the full password (all seven cycles).
11. ACC must be at V when setting PPB or DYB.
IH
12. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
66
S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
