D a t a S h e e t
Table 13. Sector Protection Commands (x16)
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Command Sequence
(Notes)
Addr
555
XX
Data
AA
Addr
2AA
XXX
Data
55
Addr
Data
Addr Data Addr Data Addr Data Addr Data
Command Set Entry (5)
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
555
40
Lock
Register
Bits
Program (6)
A0
Data
Read (6)
00
XX
Data
90
Command Set Exit (7)
Command Set Entry (5)
Program (8)
XX
2AA
PWAx
01
00
55
555
XX
AA
555
60
A0
PWDx
PWD1
03
Password
Protection
Read (9)
XXX
00
PWD0
25
02
00
PWD2
PWD0
03
01
PWD3
PWD1
Unlock (10)
00
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
Command Set Entry (5)
PPB Program (11)
All PPB Erase (11, 12)
PPB Status Read
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
XX
90
AA
XX
00
555
XX
2AA
SA
55
555
C0
A0
00
Non-Volatile
Sector
XX
SA
80
00
30
Protection (PPB)
RD(0)
90
XX
XX
2AA
XX
00
55
00
Global
Volatile Sector
Protection
Freeze
555
XX
AA
A0
555
555
50
E0
PPB Lock Bit Status Read
XXX
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
(PPB Lock)
Command Set Entry (5)
DYB Set
3
2
2
1
2
555
XX
XX
SA
XX
AA
A0
2AA
SA
55
00
01
Volatile Sector
Protection
(DYB)
DYB Clear
A0
SA
DYB Status Read
Command Set Exit (7)
RD(0)
90
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
SA = Sector Address. Any address that falls within a specified sector.
See Tables 2–4 for sector address ranges.
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If
unprotected, DQ0 = 1.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
6. No unlock or command cycles required when bank is reading
array data.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. Password may be unlocked or read in any order. Unlocking
requires the full password (all seven cycles).
11. ACC must be at V when setting PPB or DYB.
IH
12. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
64
S29GL-N MirrorBit™ Flash Family
S29GL-N_00_B3 October 13, 2006
SPANSION [ SPANSION ]
