D a t a S h e e t
Table 14. Memory Array Commands (x8)
Bus Cycles (Notes 1–5)
First
Addr
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr
Command Sequence
(Notes)
Data
RD
F0
Addr
Data
Data
Addr
Data
Data
Data
Asynchronous Read (6)
Reset (7)
1
1
4
6
4
4
1
4
6
1
3
3
2
2
2
2
6
6
1
1
3
4
1
4
RA
XXX
AAA
AAA
AAA
AAA
AA
AAA
AAA
SA
AAA
AAA
XXX
XXX
XXX
XXX
AAA
AAA
XXX
XXX
AAA
AAA
00
Manufacturer ID
AA
AA
AA
AA
98
AA
AA
29
AA
AA
A0
80
555
555
555
555
55
55
55
55
AAA
AAA
AAA
AAA
90
90
90
90
X00
X02
[SA]X04
X06
01
Device ID (8)
Sector Protect Verify (9)
Secure Device Verify (10)
XX7E
Data
Data
X1C
PA
Data
X1E
Data
CFI Query (11)
Program
555
555
55
55
AAA
PA
A0
25
PA
SA
PD
Write to Buffer (12)
Program Buffer to Flash
Write to Buffer Abort Reset (13)
Entry
WC
PD
WBL
PD
PA
555
PA
55
55
PD
30
10
00
55
55
555
AAA
F0
20
Program (14)
Sector Erase (14)
Chip Erase (14)
Reset
SA
80
SA
90
XXX
555
555
Chip Erase
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Erase/Program Suspend (15)
Erase/Program Resume (16)
Entry
AA
AA
Data
AA
555
555
55
55
AAA
AAA
88
A0
Program (17)
Read (17)
PA
PD
00
Exit (17)
AAA
555
55
AAA
90
XXX
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the falling edge of WE#
or CE# pulse, whichever occurs later.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
SA = Sector Address. Any address that falls within a specified sector.
See Tables 2–4 for sector address ranges.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 on page 13 for description of bus operations.
2. All values are in hexadecimal.
11. Command is valid when device is ready to read array data or
when device is in autoselect mode.
12. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
13. Command sequence resets device for next command after
write-to-buffer operation.
14. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return reading
array data.
15. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation.
16. Erase Resume command is valid only during the Erase Suspend
mode.
17. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data in
certain cases. See Reset Command section for details.
8. Data in cycles 5 and 6 are listed in Table 5 on page 37.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. PPB Status Read provides the same data but in
inverted form.
10. If DQ7 = 1, region is factory serialized and protected. If DQ7 =
0, region is unserialized and unprotected when shipped from
factory. See Secured Silicon Sector Flash Memory Region on
page 43 for more information.
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
65
SPANSION [ SPANSION ]
