D a t a S h e e t
16. Erase And Programming Performance
Max
(Note 2)
Parameter
Typ (Note 1)
Unit
Comments
Sector Erase Time
Chip Erase Time
0.5
32
3.5
64
Excludes 00h
programming prior
to erasure
S29GL032N
S29GL064N
sec
64
128
(Note 6)
Total Write Buffer Program Time (Notes 3, 5)
240
200
31.5
63
µs
Excludes system
level overhead
(Note 7)
Total Accelerated Effective Write Buffer Program Time (Notes 4, 5)
S29GL032N
Chip Program Time
S29GL064N
sec
Notes
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V, 10,000 cycles; checkerboard data pattern.
CC
2. Under worst case conditions of 90°C; Worst case V , 100,000 cycles.
CC
3. Programming time (typ) is 15 μs (per word), 7.5 μs (per byte).
4. Accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).
5. Write buffer Programming time is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.1 on page 51 and Table 10.3
on page 53 for further information on command definitions.
Table 16.1 TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
TSOP
BGA
CIN
Input Capacitance
VIN = 0
TBD
6
TBD
12
TSOP
BGA
COUT
CIN2
CIN3
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
VIN = 0
TBD
6
TBD
10
TSOP
BGA
TBD
27
TBD
30
TSOP
BGA
#RESET, #WP/ACC Pin Capacitance
TBD
TBD
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit® Flash Family
73
SPANSION [ SPANSION ]
