D a t a S h e e t
Figure 15.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 55.)
2. Illustration shows device in word mode.
Figure 15.8 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
DQ7
Valid Data
Valid Data
Complement
Complement
True
High Z
DQ0–DQ6
Status Data
True
Status Data
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit® Flash Family
69
SPANSION [ SPANSION ]
