D a t a S h e e t
Table 15.2 Hardware Reset (RESET#)
Parameter
JEDEC Std.
Description
All Speed Options
Unit
tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)
Max
Max
20
μs
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode
tReady
500
ns
(See Note)
tRP
tRH
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
tRPD RESET# Input Low to Standby Mode (See Note)
tRB
RY/BY# Output High to CE#, OE# pin Low
Note
Not 100% tested.
Figure 15.4 Reset Timings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRH
tRP
Notes
1. Not 100% tested.
2. See the Erase And Programming Performance on page 73 for more information.
3. For 1–16 words/1–32 bytes programmed.
66
S29GL-N MirrorBit® Flash Family
S29GL-N_01_09 November 16, 2007
SPANSION [ SPANSION ]
