P r e l i m i n a r y
Table 32. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
Manufacturer ID
1
1
4
RA
RD
F0
XXX
AAA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
(Note
17)
(Note
17)
Device ID (Note 9)
4
4
AAA
AAA
AA
AA
X1C
X1E
SecSi‰ Sector Factory
Protect (Note 10)
555
555
55
55
AAA
AAA
90
90
X06
(Note 10)
00/01
Sector Group Protect Verify
(Note 12)
4
AAA
AA
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Write to Buffer (Note 11)
Program Buffer to Flash
3
4
3
1
AAA
AAA
AAA
SA
AA
AA
AA
29
555
555
555
55
55
55
AAA
AAA
SA
88
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
Write to Buffer Abort Reset (Note
13)
3
AAA
AA
555
55
AAA
F0
Chip Erase
6
6
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (Note
14)
1
XXX
B0
Program/Erase Resume (Note
15)
1
1
XXX
AA
30
98
CFI Query (Note 16)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or AAA as shown in table, address bits above A11 are don’t
care.
10. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determined by
number of bytes written to write buffer. Maximum number of
cycles in command sequence is 37, including “Program Buffer to
Flash” command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
7. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
17. Refer to Table 14, AutoSelect Codes for individual Device IDs
per device density and model number.
114
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00A5 April 30, 2004
SPANSION [ SPANSION ]
