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S29GL064M90FFIR10 参数 Datasheet PDF下载

S29GL064M90FFIR10图片预览
型号: S29GL064M90FFIR10
PDF下载: 下载PDF文件 查看货源
内容描述: 3.0伏只页面模式闪存具有0.23微米的MirrorBit制程技术 [3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology]
分类和应用: 闪存存储内存集成电路
文件页数/大小: 160 页 / 4686 K
品牌: SPANSION [ SPANSION ]
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P r e l i m i n a r y  
Write Operation Status  
The device provides several bits to determine the status of a program or erase  
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 19 and the following subsec-  
tions describe the function of these bits. DQ7 and DQ6 each offer a method for  
determining whether a program or erase operation is complete or in progress.  
The device also provides a hardware-based output signal, RY/BY#, to determine  
whether an Embedded Program or Erase operation is in progress or has been  
completed.  
DQ7: Data# Polling  
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded  
Program or Erase algorithm is in progress or completed, or whether the device is  
in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#  
pulse in the command sequence.  
During the Embedded Program algorithm, the device outputs on DQ7 the com-  
plement of the datum programmed to DQ7. This DQ7 status also applies to  
programming during Erase Suspend. When the Embedded Program algorithm is  
complete, the device outputs the datum programmed to DQ7. The system must  
provide the program address to read valid status information on DQ7. If a pro-  
gram address falls within a protected sector, Data# Polling on DQ7 is active for  
approximately 1 µs, then the device returns to the read mode.  
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.  
When the Embedded Erase algorithm is complete, or if the device enters the  
Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must  
provide an address within any of the sectors selected for erasure to read valid  
status information on DQ7.  
After an erase command sequence is written, if all sectors selected for erasing  
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the  
device returns to the read mode. If not all selected sectors are protected, the Em-  
bedded Erase algorithm erases the unprotected sectors, and ignores the selected  
sectors that are protected. However, if the system reads DQ7 at an address within  
a protected sector, the status may not be valid.  
Just prior to the completion of an Embedded Program or Erase operation, DQ7  
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-  
serted low. That is, the device may change from providing status information to  
valid data on DQ7. Depending on when the system samples the DQ7 output, it  
may read the status or valid data. Even if the device has completed the program  
or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may  
be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.  
Table 33 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data#  
Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#  
Polling timing diagram.  
April 30, 2004 S29GLxxxM_00A5  
S29GLxxxM MirrorBitTM Flash Family  
115