A d v a n c e I n f o r m a t i o n
AC Characteristics
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erase
Resume
Erasing
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 26. DQ2 vs. DQ6 for Erase/Erase Suspend Operations
CE#
CLK
AVD#
Addresses
OE#
VA
VA
tOE
tOE
Data
Status Data
Status Data
RDY
Notes:
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation
is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY
is active one clock cycle before data.
4. Data polling requires burst access time delay.
Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings
84
S29CD032G
30606B0 March 22, 2004
SPANSION [ SPANSION ]
