A d v a n c e I n f o r m a t i o n
AC Characteristics
tWC
VA
tRC
Addresses
VA
tACC
tCE
VA
CE#
tCH
tOE
OE#
tOEH
tDF
tOH
WE#
High Z
High Z
DQ7
Data
Valid Data
Complement
Complement
True
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 24. Data# Polling Timings
(During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 25. Toggle Bit Timings
(During Embedded Algorithms)
March 22, 2004 30606B0
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SPANSION [ SPANSION ]
